1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic products. More particularly, the present invention relates to methods for forming cobalt silicide layers within microelectronic products.
2. Description of the Related Art
Common in the art of microelectronic product fabrication, and particularly in the art of semiconductor product fabrication, is the use of silicide layers. Silicide layers are desirable within microelectronic products since silicide layers generally provide low contact resistance layers within microelectronic products.
Of the types of silicide layers which may be formed within microelectronic products cobalt silicide layers are particularly desirable insofar as cobalt silicide layers generally provide low contact resistance even as contact areas diminish.
While cobalt silicide layers are thus desirable in the art of microelectronic product fabrication, cobalt silicide layers are nonetheless not entirely without problems in the art of microelectronic product fabrication. In that regard, cobalt silicide layers are often difficult to fabricate with enhanced electrical properties within microelectronic products.
It is thus desirable in the art of microelectronic fabrication to fabricate cobalt silicide layers with enhanced electrical properties.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic product fabrication for forming cobalt silicide layers with desirable properties.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Wang et al., in “New CoSi2 SALICIDE Technology for 0.1 um Processes and Below,” 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 17-18; (2) Tung et al., in “Increased uniformity and thermal stability of CoSi2 thin films by Ti capping,” Appl. Phys. Lett., 67 (15), 9 Oct. 1995, pp. 2164-66; (3) Sohn et al., in “High Thermal Stability and Low Junction Leakage Current of Ti Capped Co Salicide and its Feasibility for High Thermal Budget CMOS Devices,” IEDM 98-1005 to 98-1008; (4) Wang et al., in U.S. Pat. No. 5,780,362; and (5) Goto et al., in U.S. Pat. No. 6,197,646, all of which relate at least in part to capping layer methods for forming cobalt silicide layers. The teachings of all of the foregoing references are incorporated herein fully by reference.
Desirable in the art of microelectronic product fabrication are additional methods for fabricating cobalt silicide layers with enhanced electrical properties.
It is towards the foregoing object that the present invention is directed.